Computing devices often include numerous processors for executing various instructions/systems. For example, a smartphone mobile device may utilize an applications processor for performing routines related to a downloaded application as well as a digital signal processor for performing signaling processing operations. Such processors may each be configured to utilize a virtual memory address scheme so their respective processes may access data using simplistic memory addresses that map to various physical addresses within system memory. For example, an applications processor may utilize consecutive virtual addresses to access arbitrary RAM locations associated with data for an application.
Devices are now beginning to utilize various processors of different architectures. Such a heterogeneous system may increase the potential for software to benefit from shared memory and may utilize various application programming interfaces (APIs), such as OpenCL, Renderscript, etc. However, differences in addressing schemes may require inefficient mechanisms using conventional approaches. For example, heterogeneous system devices, such as modern smartphones, may employ both 64-bit and 32-bit processors and/or processing cores. With different architectures, the various processors may utilize different virtual memory address schemes to access the same (or shared) system memory. For example, the same page (or memory block) of RAM may be used by both a first and second processor; however, that page may be referenced by two different virtual addresses by the two processors. The processors in such heterogeneous systems may each utilize a translation lookaside buffer (TLB) that improves the speed and efficiency for accessing system memory via virtual addresses, and thus may require robust support for TLB coherency. TLBs may use many-to-one mapping of virtual pages to physical pages in system or common memory, making the coherent identification of entries expensive in terms of processing time and power consumption.
Techniques exist for maintaining coherency in a multi-core system. For example, there are API commands that modify TLB entries using virtual addresses, such as Linux ARM TLB flush methods flush_tlb_all( ) flush_tlb_mm(memory_block_identifier), flush_tlb_range(memory_block_identifier, start_index, end_index), and flush_tlb_page(virtual_address, virtual_mask). As another example, some systems may perform a TLB “shoot-down” technique that utilizes virtual addresses for look-up and invalidation operations for entries within TLBs. A typical TLB shoot-down procedure may include a first processor sending an interrupt to a second processor including a virtual address to be invalidated in the second processor's page table.